Wireless devices have been in use for many years for enabling mobile communication of voice and data. Such devices can include mobile phones and wireless enabled personal digital assistants (PDA's) for example. FIG. 1 is a generic block diagram of the core components of such wireless devices. The wireless core 10 includes a base band processor 12 for controlling application specific functions of the wireless device and for providing and receiving voice or data signals to a radio frequency (RF) transceiver chip 14. The RF transceiver chip 14 is responsible for frequency up-conversion of transmission signals, and frequency down-conversion of received signals. RF transceiver chip 14 includes a receiver core 16 connected to an antenna 18 for receiving transmitted signals from a base station or another mobile device, and a transmitter core 20 for transmitting signals through the antenna 18. Those of skill in the art should understand that FIG. 1 is a simplified block diagram, and can include other functional blocks that may be necessary to enable proper operation or functionality.
Generally, the transmitter core 20 is responsible for up-converting electromagnetic signals from base band to higher frequencies for transmission, while receiver core 16 is responsible for down-converting those high frequencies back to their original frequency band when they reach the receiver, processes known as up-conversion and down-conversion (or modulation and demodulation) respectively. The original (or base band) signal may be, for example, data, voice or video. These base band signals may be produced by transducers such as microphones or video cameras, be computer generated, or transferred from an electronic storage device. In general, the high frequencies provide longer range and higher capacity channels than base band signals, and because high frequency radio frequency (RF) signals can propagate through the air, they are preferably used for wireless transmissions as well as hard-wired or fibre channels.
All of these signals are generally referred to as radio frequency (RF) signals, which are electromagnetic signals; that is, waveforms with electrical and magnetic properties within the electromagnetic spectrum normally associated with radio wave propagation.
FIG. 2 is a circuit diagram of a direct conversion receiver core that can be used in the wireless transceiver 10 of FIG. 1. As shown in FIG. 2, the receiver core 16 can include a low noise amplifier 30, a mixer 32, a variable gain amplifier (VGA) 34, a filter 36, an analog to digital converter (ADC) 38 and a digital processing circuit 40. VGA 34, filter 36, ADC 38 and digital processing circuit 40 can be considered signal processing circuitry since they collectively condition the RF input signal RFin for use by downstream circuits such as the baseband processor. While not expressly shown in the circuit of FIG. 2, those skilled in the art should understand that there are separate i and q signal propagation paths. This listing of components in receiver core 16 is not comprehensive, and any person of skill in the art will understand that the specific configuration will depend on the communication standard being adhered to and the chosen receiver architecture.
The general operation of the receiver core 16 is as follows. An RF input signal RFin is amplified by low noise amplifier 30, and then down-converted to baseband frequency R_CLK by mixer 32. This down-converted baseband signal is amplified to a desired level of gain by variable gain amplifier 34 in response to the level of gain control voltage VCONT, and then filtered through filter 36 to reduce the dynamic range of the signal. The resulting output signal is then converted to a digital signal D_SIGNAL by ADC 38. The digital signal D_SIGNAL can now be further processed in the digital domain by downstream circuits, such as digital processing circuit 40. In most configurations, digital processing circuit 40 provides a digital signal Dig_Out to the baseband processor.
In the presently shown direct conversion receiver core 16, a problem is the generation of second order intermodulation products (IIP2), which originates from mixer 32. An explanation of where IIP2 is generated follows with reference to FIGS. 3 and 4.
An example of a known differential mixer circuit is shown in FIG. 3. This differential mixer can be used as mixer 32 in FIG. 2. Differential pair mixer circuit 50 is an active mixing circuit, which includes a load resistor R1 and n-channel transistor 52 connected in series between a voltage supply VCC and a drain terminal of input n-channel transistor 54, and a load resistor R2 and n-channel transistor 56 connected in series between VCC and the same drain terminal of input n-channel transistor 54. The gate terminal of n-channel transistor 52 receives the signal z, and the gate terminal of n-channel transistor 54 receives the complement of the signal z denoted as z*. The gate terminal of input n-channel transistor 54 receives RF input signal x, and its source terminal is connected to VSS. The resulting complementary output signals y and y* are taken from the drain terminals of n-channel transistors 52 and 56 respectively. One output path 58 of mixer circuit 50 is between the drain of input n-channel transistor 54 and the node y, while the other output path 60 is between the drain of input n-channel transistor 54 and the node y*. In the context of mixer 32 of FIG. 2, signal x is equivalent to RFin, signals z and z* are equivalent to R_CLK and its complement R_CLK*, and signals y and y* are equivalent to the outputs of mixer 32.
A problem with this circuit lies in the non-linear nature of input transistor 54, which will generate an output y/y* having undesired intermodulation products. The current “I” through input transistor 54 can be expressed in equation (1) below:I=gm*Vx, where gm is the transconductance and Vx is the voltage of input signal x  (1)
However, since gm of transistor 54 is a non-linear, the actual current “I” will be expressed by equation (2):I=a1Vx+a2Vx2+a3Vx3+a4Vx4  (2)
where a1, a2, a3 and a4 are coefficients, and terms from a2 and on are considered nth order intermodulation products.
The effect of the intermodulation products can be seen in the output y(t) of the mixer circuit 50 downconverted to baseband by z(t), which has a large frequency component at the RF signal frequency. FIG. 4a shows an input signal, x(t) made up of two tones ω1 and ω2. FIG. 4b shows the signal z(t), having a frequency tone at ωz used to down convert the signal x(t). After down conversion, the tones ω1 and ω2 are displaced by ωz. FIG. 4c shows the displacement of ω1 and ω2 as ω1−ωz and ω2−ωz respectively. The tone ω1−ω2 is generated by the second order term in equation (2) along with mismatches in 52 and 56 or R1 and R2. This tone effectively degrades the SNR of the radio. Thus, to mitigate the effect of second order intermodulation products, the linear relationship is ideally maintained by ensuring that all coefficients other than a1 are zero, so that those terms will disappear.
However, because mixer circuit 50 is a differential-type circuit, the a2 coefficient should be inherently reduced to zero. Differential circuits such as the one shown in FIG. 3 generally have two complementary data paths that should inherently cancel out any distortion components that may be introduced in them. In ideal conditions, differential-type circuits will set all even order terms a2, a4, a6 etc.=0.
In practice however, the even order terms will cancel only if the two complementary data paths are identically matched. In mixer circuit 50 of FIG. 3 for example, the even order terms will cancel the characteristics of both resistors R1 and R2 are identical (ie. R1=R2), the electrical characteristics of both transistors 52 and 56 are identical, and the connections between transistor 54 to 52 and 54 to 56 are identical. In this situation both data paths can be considered matching. Therefore the second order intermodulation products should be inherently cancelled out.
However, this situation is ideal, and in practice the two data paths 58 and 60 are not electrically identical to each other. Semiconductor circuit layout and/or slight process variations and/or anomalies across the chip can introduce mis-match between the two paths. With reference to FIG. 3, the two load resistors can have slightly different values, or transistors 52 and 56 can have slightly differing doping levels or dimension differences, or un-balanced parasitic capacitance on the connections between the transistors, which are sufficient to cause mis-match in the paths. This mis-match can cause the second order intermodulation products to appear. The data path mismatch can be compensated for by trimming one or both load resistors, or by digitally switching in different valued resistors that are pre-formed on the chip. This is typically done during testing of the fabricated devices by detecting and measuring the amplitudes of the second order intermodulation products, and then selecting the appropriate resistor that minimizes the magnitude of the second order intermodulation products.
Another known scheme of minimizing second order intermodulation products is balancing, or matching, the complementary output paths of a mixer by directly adding or removing current from one of the paths. One example of a suitable scheme for minimizing second order intermodulation products in differential mixers is disclosed in commonly owned U.S. patent application Ser. No. 11/298,667, the entire contents of which are incorporated by reference.
In accordance with the scheme shown in U.S. patent application Ser. No. 11/298,667, mixer 32 of FIG. 2 receives an IIP2 compensation signal COMP for balancing its differential signal paths. Depending on the particular IIP2 minimizing scheme being used, COMP can be one or more digital or analog signals. With respect to the embodiments of the present invention, any IIP2 minimizing scheme can be employed.
Regardless of the IIP2 minimizing scheme employed, prior to application of an IIP2 compensation signal the wireless device must be tested for measuring or quantifying the amount of IIP2 being generated. Then the appropriate IIP2 compensation signals are generated and provided to the IIP2 minimizing scheme being employed.
FIG. 5 is a flow chart illustrating a generic IIP2 testing method for measuring IIP2 from a wireless device to be used in conjunction with an IIP2 minimizing scheme. Generally, the test involves application of an input signal to the chip, measuring the IIP2, and then applying some signal compensation to minimize the IIP2. It is assumed that the parameter being measured is a parameter compatible with a particular IIP2 minimizing scheme. This method is applied to a fabricated wireless device, such as a wireless transceiver chip, or a wireless system incorporating the wireless transceiver chip such as a mobile phone for example.
The method starts at step 70 where a test input signal is applied to an input port of the chip or system. Test signals can be generated with widely available testing equipment, and customized to include a second order tone. This is typically the same input through which a received RF signal will propagate to the receiver core. Alternately, the test input signal can be applied through a specific test input port. The entry point of the test signal is not important, as long as it is applied before the source of IIP2 generation and compensation. In the example receiver core 16 of FIG. 2, the input test signal can be applied before mixer 32. Alternately, the input test signal can be applied at the input of the low noise amplifier 30 or at the antenna port.
At step 72, the output of the chip or system is evaluated and the IIP2 parameter is measured. An appropriate compensation code or signal is generated at step 74, which is then applied to the IIP2 minimizing scheme, which then adjusts α2=a2 to be zero. Fuses or other suitable programming means can be used for permanently storing the specific IIP2 compensation signal code either on chip or in the system.
Proceeding to step 76 after the compensation code is generated, if there are further chips or systems to test, then the method returns to step 70 for a subsequent testing loop for the next chip or system. This testing method repeats until there are no further chips or systems to test.
As previously mentioned, this method can be used for testing individual chips prior to packaging, or entire systems. At the chip level, each chip is tested, and the appropriate compensation programming is applied. For example, the programming can be done by blowing particular on-chip fuses or storing the appropriate compensation code in non-volatile memory prior to packaging. Alternately, each packaged chip can be tested and a corresponding compensation code is generated. This code can be used at the system level to compensate for the measured IIP2. At the system level, the IIP2 is measured as a function of the entire phone, and appropriate compensation circuits in the system can be appropriately enabled to minimize IIP2.
While the previously described method of FIG. 5 is effective for testing wireless chips and systems and minimizing IIP2, it is not very practical. In particular, the method is very cumbersome and time consuming to implement. This is due to the fact that circuit mismatch can vary from chip to chip, and accordingly, the IIP2 of each chip (or system) must be measured, and a corresponding compensation code valid only for that chip (or system) is provided. Moreover, relatively expensive test equipment such as signal generators and chip/system test apparatus are required. This cost increases if high testing throughput is required, otherwise testing will be time consuming. Therefore, IIP2 testing and compensation is both economically and/or time consuming.
BIST (built-in-self-test) schemes are presently used in other semiconductor systems, such as memory devices and controllers for example. Such self-testing is automatically executed by the chip, and can relieve the burden of using external test equipment and time for testing since the chip will have the necessary test circuits implemented thereon.
However, there are no known BIST schemes adapted for self-testing IIP2 and auto calibration in response to the measured IIP2. For self-contained test and IIP2 calibration, a test signal must be generated, in the same way that a test signal is applied in the testing scheme shown in FIG. 5. However, the addition of test signal generator circuits onto a wireless transceiver can consume substantial silicon area of the chip. Because the area of wireless transceiver devices should be minimized to make them attractive for high system integration in portable applications, such as mobile phones, the increase in chip area is undesired. Furthermore, as those skilled in the art will understand, an increased chip size will directly increase the cost for manufacturing the chip.
It is, therefore, desirable to provide a IIP2 calibration scheme that reduces testing time while minimizing the amount of additional on-chip circuits.